1. Field of the Invention
The present invention relates to integrated circuits in general and more particularly to circuit arrangements for biasing selected devices on Very Large Scale Integration (VLSI) chips.
2. Prior Art
Most VLSI chips are being designed with CMOS technology. It is believed that this trend is an attempt to capitalize on the improved power and performance characteristics which the CMOS technology provides. A typical VLSI chip is made up of thousands of circuit arrangements integrated on a single substrate. Some of these circuits, such as programmable logic arrays (PLA), bus with several dotted drivers, etc., require static power dissipating circuits in order to ensure proper operation.
One of the disadvantages of these static circuits is that, at worst case, they dissipate a relatively large amount of power. Because CMOS technology is a low power technology, the presence of static circuits on the CMOS chip negates or undermines one of the benefits associated with the CMOS technology. Even though there are a plurality of different types of static CMOS circuits, an inverter circuit will be used to illustrate the relatively large amount of power which a typical static CMOS circuit dissipates.
FIG. 1 shows a circuit schematic of two typical inverter circuits which include a pair of P-channel devices Q26, Q30, and a pair of N-channel devices Q28, Q32. The source electrodes of the P-channel devices are connected to power supply (Vps) and the source electrodes of the N-channel devices are connected to ground potential. As is the usual practice with static CMOS circuits without availability of depletion NMOS devices, P-channel FET device (Q26) is used as the load device. To effectuate the loading function, the gate electrode of Q1 is connected to the ground potential.
Current in the P-channel device can be expressed by the following simplified equation. EQU I=K(Vgate-Vs-Vt).sup.2,
where
K is a function of parameters such as device width, length, gate oxide thickness, etc. PA1 Vgate is the gate voltage of the P-channel device PA1 Vs is the source of the device, the power supply Vps PA1 Vt is the threshold voltage of the device, typically -1 volt PA1 For the P-channel device shown (Vgate-Vs)=Vps PA1 Vps is the power supply voltage typically 5.+-.10%.
Variations in the process parameters cause K to vary by as much as +/-60% between its -3 sigma limit and its +3 sigma limit. Varying the power supply voltage Vps from 4.5 volts to 5.5 volts increases the current in the P-channel device by 50%. Combining process variations and power supply tolerance, the current in the device can vary more than 400% from worst case (-3 sigma limit) to best case (+3 sigma limit). The -3 sigma and +3 sigma limits are statistical terms used to describe standard deviation from a nominal value.
Circuit performance can improve by a factor of 4 between worst case conditions and best case conditions. The designer usually has a worst case performance target for the circuit being designed. The designer then must be able to accommodate the power dissipation of the circuit at best case conditions. If there is a significant number of static circuits on a VLSI chip, the power dissipation at best case conditions will raise the chip's junction temperature, reduce its reliability and decrease the performance of other circuits.
A straightforward approach for solving the power dissipation problem is to package the chip in a ceramic casing. Such casing usually has lower thermal resistance which keeps the junction temperature lower. Ceramic packages have lower thermal resistance than plastic packages but are more expensive and will make the component less competitive in the market place. In addition, the increased current stresses the current density limits of metal and contact structures further compounding the reliability issues.